1. Field of the Invention
The present invention relates to a motion detection circuit for use in a television and, more particularly, to a circuit for detecting the motion of an image with respect to each pixel of the image.
2. Description of the Prior Art
One motion detection circuit 100 known in the prior art is shown in FIG. 1, which includes a low pass filter (LPF) 41, high pass filter (HPF) 46 frame memories 42, 47, 48 each of which delays the signal one frame period, subtracters 43, 49, absolute value circuits 44, 50, threshold circuits 45, 51 which compare the magnitude of the signal input thereto with a predetermined threshold, and logic circuit 52 which determines whether or not the image at each pixel has been changed.
In the operation of the circuit of FIG. 1, the NTSC signal is input from terminal 40 to LPF 41 and also to HPF 46. The LPF 41 passes the low frequency component of the NTSC signal, i.e., the low frequency luminance signal, to the frame memory 42. At the subtracter 43, the low frequency luminance signal which is not delayed is subtracted from the one frame delayed low frequency luminance signal, and the absolute value of the subtracter 43 output is obtained at the absolute value circuit 44. This operation is carried out for each pixel.
Because the two signals used for subtraction at subtracter 43 represent the same pixel position on the screen but delayed one frame, these two signals will be identical when the image at the pixel position is a still image, and the output of the absolute value circuit 44 is therefore zero. However, when there is motion in the image, the frame delayed signals differ, and a value other than zero is output from the absolute value circuit 44.
The output of the absolute value circuit 44 is compared with a threshold value by the threshold circuit 45. If the threshold value is smaller than the value produced from the absolute value circuit 44 it is assumed that the image at the corresponding pixel position is moving. In this case, threshold circuit 45 produces an output "1". However, if the threshold is greater, the image at the pixel position is assumed to be a still image. In this case, threshold circuit 45 produces an output "0".
The HPF 46 outputs a high frequency video signal in which the high frequency luminance signal and the chrominance subcarrier signal are mixed. This high frequency video signal is input sequentially to the two frame memories 47, 48. At subtracter 49 the undelayed high frequency video signal is subtracted from the delayed high frequency video signal. Since the phase of the chrominance subcarrier reverses every frame, the chrominance subcarrier signals with the same phase are subtracted at subtracter 49. The output of the subtracter 49 is input sequentially to the absolute value circuit 50 and the threshold circuit 51 as described above. The output from the threshold circuit 51 is "0" for a still image and "1" for a motion image, in a similar manner as described above.
The logic circuit 52 outputs a "1" when the output of at least one of the threshold circuits 45, 51 is producing "1". Specifically, the logic circuit 52 detects motion when motion is detected in either the low frequency luminance signal or the high frequency image signal, and in such a case, logic circuit 52 outputs "1".
Another motion detection circuit 200 known in the art is shown in FIG. 2, which includes a 262 H period delay 61 which delays the input signal 262 lines, subtracters 62, 65, a frame memory 64, absolute value circuits 63, 66, and threshold circuit 67.
In the operation of the circuit of FIG. 2, when the NTSC signal is input to terminal 60, the undelayed signal is subtracted from the 262 line delayed signal by the subtracter 62. Since the phase of the chrominance subcarrier applied directly from terminal 60 to subtracter 62 and that applied through 262 H delay 61 to subtracter 62 is the same, and since the 262 H delay is substantially equal to a difference between, e.g., one odd line and the neighboring even line, as shown in FIG. 3, subtracter 62 subtracts the data at pixel position P2 from the data at pixel position P1 (P1 and P2 also represent signal levels obtained at respective positions). Thus, the output from the subtracter 62 includes the vertical difference of the signals in a two-dimensional field in addition to the difference caused by the image movement. The difference signal (P1-P2) from subtracter 62 is input to the absolute value circuit 63 whereby the absolute value .vertline.P1-P2.vertline. of the signal is obtained. The output of the absolute value circuit 63 is input to the frame memory 64 and also to subtracter 65. Thus, the difference between the signal .vertline.P1'-P2'.vertline. delayed one frame and the signal .vertline.P1-P2.vertline. not delayed is obtained from the subtracter 65. The difference signal {.vertline.P1'-P2'.vertline.}-{.vertline.P1-P2.vertline.} output from the subtracter 65 is input to the absolute value circuit 66 whereby the absolute value of the signal is obtained, and the result is input to the threshold circuit 67.
FIG. 4 shows the relationship between the sampling point in each field and the phase of the subcarrier at that point. In FIG. 4, S0 represents a sampling point in field n, and S1 and S2 are sampling points in field n+1. S1 appears one line above S2 on the screen. S3 represents a sampling point in field n+2, and S4 a sampling point in field n+3. The direction of the arrow shown at each sampling point indicates the phase of the subcarrier; S0 and S1 have the same phase; S2, S3, and S4 each have the same phase, but are of an opposite phase relative to S0 and S1.
When the signal input from the input terminal 60 carries a still image, the difference signal output from the subtracter 62 is the difference of S0 and S1 in FIG. 3, indicating only the difference of the signals in the vertical of the two directions. When the image at the checking area CA is a still image, the two-dimension difference signal, such as .vertline.S0-S1.vertline., is the same as that .vertline.S3-S4.vertline. obtained in the following frame, and the output from the subtracter 65 is therefore zero.
Furthermore, when the signal input from the terminal 60 carries a motion image, the difference signal, such as (S0-S1), output from the subtracter 62 is still the difference in the vertical (two-dimension) and now includes information indicating motion in the image. The information indicating motion is detected by subtracter 65, such that the output from the subtracter 65, .vertline..vertline.S0-S1.vertline.-.vertline.S3-S4.vertline..vertline., will not be zero because the difference signal will result from a different pattern in the next frame.
A conventional luminance signal/chrominance signal separation circuit using the motion detection circuit 100 or 200 described above is shown in FIG. 5.
The luminance signal/chrominance signal separation circuit includes a frame filter 71 which separates the chrominance signal using the perceived picture elements and the picture elements one frame period away, a two-dimensional filter 73 which separates the chrominance signal using the perceived picture elements and the proximal picture elements in the same field, the motion detection circuit 100 or 200 such as shown in FIG. 1 or FIG. 2, a switching circuit 72, a high pass filter (HPF) 74, and a subtracter 75.
According to the luminance signal/chrominance signal separation circuit shown in FIG. 5, when the video signal is input from the input terminal 70, the chrominance signals C1 and C2 are separated by the frame filter 71 and the two-dimensional filter 73, respectively. When the image is a still image, signal C1 is completely separated with hardly any defect. However, when the image is a motion image, C1 contains ghost image data and other image degradations such as artifact (including dot crawl and cross color) which will not be observed in the C2 signal. On the other hand, the C2 signal contains no new degradation whether the image is a still or motion image, although it is not a completely separated signal.
Furthermore, the switching circuit 72 selects C1 for still images or C2 for motion images according to the output from the motion detection circuit 100 or 200, and thus selects the chrominance signal with the least deterioration. The chrominance signal selected by the switching circuit 72 is limited to the high frequency band by the HPF 74, and is subtracted from the source signal by the subtracter 75 to obtain the luminance signal.
However, when an image with a pattern of vertical stripes in the high frequency component as shown in FIGS. 6a and 6b moves horizontally, the striped pattern in field n will be the precise reverse of that in field n+2 at a certain speed. This is further illustrated in detail in FIG. 6c.
FIG. 6c shows the sampling points in the horizontal direction for fields n, n+1, n+2, and n+3. As shown in field n, the vertical stripes are formed by a repeated pattern of four successive black and four successive white dots. If the sampling points move two points horizontally in each field, the field n+2 has a pattern which is the inverse of the black and white patter of field n, resulting in the same phase relationship as the chrominance signal.
For the purpose of description, four sampling points at the same level in the horizontal direction in each field have been labelled S01 to S34 as shown in FIG. 6c.
When this signal is input to the prior art motion detection circuit 100 of FIG. 1, no signal will pass through the LPF 41, and therefore, absolute circuit 44 always produces zero, because the signal for the vertical stripe has a high frequency component only. Thus, the motion detection must be based on the output of the HPF 46 only. As shown in FIG. 6c, this signal inverts every field, and signals two frames apart thus have the same phase. The output from the subtracter 49 is therefore zero, and the image carried by this signal is erroneously determined to be a still image.
When this same signal is input to the second prior art motion detection circuit 200 described above with reference to FIG. 2, the output from the subtracter 62 is also zero when S32 in field n+3 and S22 in field n+2 are used as sampling points, because these sampling points have the same phase. Furthermore, the output of the subtracter 65 is also zero because the output .vertline.S02-S12.vertline. from the frame memory 64 is equal to the output .vertline.S22-S32.vertline. from the absolute value circuit 63.
When the sampling point S33 of field n+3 and S23 of field n+2 are input to the subtracter 62, the output of the subtracter 62 has a value .vertline.S23-S33.vertline. which is not equal to zero because these two points are in reverse phase. However, the output of the frame memory 64 is equal to .vertline.S03-S13.vertline., which is the same level as .vertline.S23-S33.vertline., and therefore, the output of the subtracter 65 is zero. The second prior art motion detection circuit 200 of FIG. 2 thus erroneously determines that the image represented by the signal shown in FIGS. 6a and 6b is a still image.
As thus described, both the first and second prior art motion detection circuits of FIGS. 1 and 2 described hereinabove present a problem in that a pattern represented by the signal shown in FIGS. 6a and 6b will be erroneously evaluated as a still image when the signal is input to the circuit.
Thus, when the signal shown in FIGS. 6a and 6b is input to the luminance signal/chrominance signal separation circuit of FIG. 5 using either one of motion detection circuits of FIGS. 1 and 2, the image of FIGS. 6a and 6b is detected as a still picture. Thus, the frame filter output C1 is used even when the signal represents a motion image of FIGS. 6a and 6b. This results in introducing dot crawl, ghosts, and other image degradation.